High-Gain Vector Multipliers
MAX2047 ELECTRICAL CHARACTERISTICS
( Typical Operating Circuit as shown in Figure 1; V CC = 4.75V to 5.25V, T A = -40 ° C to +85 ° C, R BIAS = 280 ? , f IN = 915MHz, input cur-
rent range = 0 to 4mA (if using a current-mode DAC), and differential input voltage range = 0 to 0.707V (if using a voltage-mode
DAC). If using a current-mode DAC, voltage mode I/Q inputs are left open. If using a voltage-mode DAC, all current-mode I/Q inputs
are left open. Typical values are at V CC = 5V and T A = +25 ° C, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER
Frequency Range
CONDITIONS
MIN
790
TYP
MAX
1005
UNITS
MHz
RF Input Return Loss
RF Output Return Loss
VOLTAGE MODE
VI = VQ = 0.707V (radius = 1V)
-21.8
-11.7
8.4
dB
dB
Power Gain
Power-Gain Range
Reverse Isolation
VI = VQ = 0.5V (radius = 0.707V)
VI = VQ = 0.25V (radius = 0.35V)
VI = VQ = 0.125V (radius = 0.175V)
Difference in gain between VI = VQ = 0.707V and
VI = VQ = 0.125V
Over entire control range
5.1
-0.9
-6.3
14.7
-75
dB
dB
dB
Maximum Power Gain for
Continuous Coverage of Phase
0 to 360 ° (radius = 1V)
7.1
dB
Change
Maximum Power Gain with
Reduced Phase Coverage
Group Delay
Gain Drift Over Temperature
0 to 360 ° (radius = 1V)
VI = VQ = 0.707V (radius = 1V)
VI = VQ = 0.707V (radius = 1V)
GSM, f IN = 942.5MHz
± 62.5MHz
8.4
2.02
-0.024
± 0.25
dB
ns
dB/ ° C
Gain Flatness Over Frequency
VI = VQ = 0.707V
(radius = 1V)
US cell, f IN = 881.5MHz
± 62.5MHz
JCDMA, f IN = 850MHz
± 60MHz
± 0.13
± 0.1
dB
KDI/JDC/PDC, f IN = 820MHz
± 30MHz
GSM, f IN = 942.5MHz
± 62.5MHz
± 0.1
± 0.9
Phase Flatness Over Frequency
Electrical delay removed ,
VI = VQ = 0.707V (radius
= 1V)
US cell, f IN = 881.5MHz
± 62.5MHz
JCDMA, f IN = 850MHz
± 60MHz
± 1.1
± 1.2
Degrees
KDI/JDC/PDC, f IN = 820MHz
± 30MHz
± 0.3
6
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